Dividers

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a lower speed version of the input clock. Available divider ratios are 2, 4, 8 and • Integrated programmable clock divider and 1:2 fanout buffer\n• Guaranteed AC performance over temperature and voltage:\n• >2.0GHz fMAX\n• <190ps tr/tf\n• <15ps within device skew\n• Low jitter design:\n• <10psPP total jitter\n• <1psRMS cycle-to-cycle jitter\n• Unique input termination and VTPin fo;

3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER W/ INTERNAL TERMINATION

文件：109.82 Kbytes Page：10 Pages

3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS

文件：144.36 Kbytes Page：10 Pages

3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS

文件：144.36 Kbytes Page：10 Pages

3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS

文件：144.36 Kbytes Page：10 Pages

3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER W/ INTERNAL TERMINATION

文件：109.82 Kbytes Page：10 Pages

3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER W/ INTERNAL TERMINATION

文件：109.82 Kbytes Page：10 Pages

3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS

文件：144.36 Kbytes Page：10 Pages

封装/外壳：16-VFQFN 裸露焊盘，16-MLF® 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK BUFFER 1:2 2GHZ 16MLF 集成电路（IC） 时钟缓冲器，驱动器

封装/外壳：16-VFQFN 裸露焊盘，16-MLF® 包装：卷带（TR） 描述：IC CLK BUFFER 1:2 2GHZ 16MLF 集成电路（IC） 时钟缓冲器，驱动器

3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER W/ INTERNAL TERMINATION

文件：109.82 Kbytes Page：10 Pages

3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS

文件：144.36 Kbytes Page：10 Pages

3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER W/ INTERNAL TERMINATION

文件：109.82 Kbytes Page：10 Pages