Dividers

This 3.3V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC- or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. Th • Guaranteed AC performance\n• >2.0GHz fMAX output toggle\n• >3.0GHz fMAX input\n• <800ps tPD (matched-delay between banks)\n• <15ps within-device skew\n• <190ps rise/fall time\n• Low jitter design\n• <1psRMS cycle-to-cycle jitter\n• Unique input termination and VTpin for DC-coupled and AC-coupled i;

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS

文件：111.68 Kbytes Page：11 Pages

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TERMINATION

文件：103.54 Kbytes Page：11 Pages

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS

文件：111.68 Kbytes Page：11 Pages

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS

文件：111.68 Kbytes Page：11 Pages

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TERMINATION

文件：103.54 Kbytes Page：11 Pages

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TERMINATION

文件：103.54 Kbytes Page：11 Pages

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS

文件：111.68 Kbytes Page：11 Pages

封装/外壳：16-VFQFN 裸露焊盘，16-MLF® 包装：卷带（TR） 描述：IC CLK BUFFER 1:3 2GHZ 16MLF 集成电路（IC） 时钟缓冲器，驱动器

封装/外壳：16-VFQFN 裸露焊盘，16-MLF® 包装：管件 描述：IC CLK BUFFER 1:3 2GHZ 16MLF 集成电路（IC） 时钟缓冲器，驱动器

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TERMINATION

文件：103.54 Kbytes Page：11 Pages

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TERMINATION

文件：103.54 Kbytes Page：11 Pages

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS

文件：111.68 Kbytes Page：11 Pages