Dividers

This 2.5V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The • Guaranteed AC performance over temperature and voltage:\n• >2GHz fMAX\n• <750ps tPD (matched delay between banks)\n• <15ps within-device skew\n• <200ps rise/fall time\n• Low jitter design\n• 265 RMS phase jitter\n• Unique input termination and VTpin for DC-coupled and AC-coupled inputs: any differ;

2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION

文件：575.32 Kbytes Page：10 Pages

2.5V, 2GHz ANY DIFF. IN-TO-LVDS

文件：178.53 Kbytes Page：10 Pages

2.5V, 2GHz ANY DIFF. IN-TO-LVDS

文件：178.53 Kbytes Page：10 Pages

2.5V, 2GHz ANY DIFF. IN-TO-LVDS

文件：178.53 Kbytes Page：10 Pages

2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION

文件：575.32 Kbytes Page：10 Pages

2.5V, 2GHz ANY DIFF. IN-TO-LVDS

文件：178.53 Kbytes Page：10 Pages

2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION

文件：575.32 Kbytes Page：10 Pages

封装/外壳：16-VFQFN 裸露焊盘，16-MLF® 包装：托盘 描述：IC CLK BUFFER 1:3 2GHZ 16MLF 集成电路（IC） 时钟缓冲器，驱动器

2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION

文件：575.32 Kbytes Page：10 Pages

封装/外壳：16-VFQFN 裸露焊盘，16-MLF® 包装：卷带（TR） 描述：IC CLK BUFFER 1:3 2GHZ 16MLF 集成电路（IC） 时钟缓冲器，驱动器

2.5V, 2GHz ANY DIFF. IN-TO-LVDS

文件：178.53 Kbytes Page：10 Pages

2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION

文件：575.32 Kbytes Page：10 Pages