5V/3.3V 첨2, 첨4, 첨8 Clock Generation Chip

General Description The SY10/100EL34/L are low-skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low-skew clock generation applications. The internal dividers are synchronous to each other; therefore, the common output edges are all precisely aligned. The devices can be driven by eit

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC CLK GEN /2/4/8 3.3/5V 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

5V/3.3V 첨2, 첨4, 첨8 Clock Generation Chip

General Description The SY10/100EL34/L are low-skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low-skew clock generation applications. The internal dividers are synchronous to each other; therefore, the common output edges are all precisely aligned. The devices can be driven by eit

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC CLK GEN /2/4/8 3.3/5V 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

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Clock Generation Chip

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