5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER w/o ENABLE

DESCRIPTION The SY10/100E111A/L are low skew 1-to-9 differential driver designed for clock distribution in mind. The SY10/100E111A/Ls function and performance are similar to the popular SY10/100E111, with the improvement of lower jitter and the added feature of low voltage operation. It accepts o

5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/o ENABLE)

文件：76.38 Kbytes Page：6 Pages

5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER w/o ENABLE

DESCRIPTION The SY10/100E111A/L are low skew 1-to-9 differential driver designed for clock distribution in mind. The SY10/100E111A/Ls function and performance are similar to the popular SY10/100E111, with the improvement of lower jitter and the added feature of low voltage operation. It accepts o

5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/o ENABLE)

文件：76.38 Kbytes Page：6 Pages

ECL/PECL 1:9 Differential Clock Driver

DESCRIPTION The AZ10/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q¯ outputs HIGH.

1:9 Differential Clock Driver

[ARIZONA MICROTEK, INC.] DESCRIPTION The AZ10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or single-ended if the VBB output is used. The signal is fanned-out to 9 identical differential

ECL/PECL 1:9 Differential Clock Driver

DESCRIPTION The AZ10/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q¯ outputs HIGH.

1:9 DIFFERENTIAL CLOCK DRIVER

Description The MC10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable i

5V ECL 1:9 Differential Clock Driver

文件：143.51 Kbytes Page：10 Pages