ENHANCED 4-STAGE COUNTER/SHIFT REGISTER

DESCRIPTION The SY100S336A is functionally the same as the SY100S336, but has Sn to TC speed and Sn set-up and hold times significantly improved, allowing for higher clock frequency when used as a cascaded multi-stage counter. FEATURES ■ Max. shift frequency of 700MHz ■ Clock to Q delay max. o

ENHANCED 4-STAGE COUNTER/SHIFT REGISTER

文件：126.53 Kbytes Page：10 Pages

封装/外壳：24-CQFlatPack，CerPack 包装：散装 描述：IC COUNTER/SHIFT REG 24-CERPAC+G 集成电路（IC） 专用逻辑器件

4-STAGE COUNTER/ SHIFT REGISTER

DESCRIPTION The SY100S336 functions either as a modulo-16 up/down counter or as a 4-bit bidirectional shift register and is designed for use in high-performance ECL systems. Three Select inputs (Sn) are provided for determining the mode of operation. The Function Table lists the available modes o

4-STAGE COUNTER/SHIFT REGISTER

文件：126.15 Kbytes Page：10 Pages

ENHANCED 4-STAGE COUNTER/SHIFT REGISTER

文件：126.53 Kbytes Page：10 Pages

ENHANCED 4-STAGE COUNTER/SHIFT REGISTER

DESCRIPTION The SY100S336A is functionally the same as the SY100S336, but has Sn to TC speed and Sn set-up and hold times significantly improved, allowing for higher clock frequency when used as a cascaded multi-stage counter. FEATURES ■ Max. shift frequency of 700MHz ■ Clock to Q delay max. o

ENHANCED 4-STAGE COUNTER/SHIFT REGISTER

文件：126.53 Kbytes Page：10 Pages