Flip Flops, Registers Products

The SY10/100E451 offer six D-type flip-flops with singleended outputs and differential data and clock inputs, designed for use in new, high-performance ECL systems.The registers are triggered by the rising edge of the CLK input. A logic HIGH on the Master Reset (MR) input resets all outputs to a log ·1100MHz min. toggle frequency\n·Extended 100E VEE range of -4.2V to -5.5V\n·Differential inputs: data and clock\n·VBB output for single-ended use\n·Asynchronous Master Reset\n·Fully compatible with industry standard 10KH, 100K ECL levels\n·Internal 75KΩ input pulldown resistors\n·Fully compatible w;

6-BIT REGISTER DIFFERENTIAL DATA CLOCK

文件：63.57 Kbytes Page：4 Pages

6-BIT REGISTER DIFFERENTIAL DATA CLOCK

DESCRIPTION The SY10/100E451 offer six D-type flip-flops with single-ended outputs and differential data and clock inputs, designed for use in new, high-performance ECL systems. The registers are triggered by the rising edge of the CLK input. FEATURES ■ 1100MHz min. toggle frequency ■ Extended

6-BIT REGISTER DIFFERENTIAL DATA CLOCK

DESCRIPTION The SY10/100E451 offer six D-type flip-flops with single-ended outputs and differential data and clock inputs, designed for use in new, high-performance ECL systems. The registers are triggered by the rising edge of the CLK input. FEATURES ■ 1100MHz min. toggle frequency ■ Extended

6-BIT REGISTER DIFFERENTIAL DATA CLOCK

文件：63.57 Kbytes Page：4 Pages

6-BIT REGISTER DIFFERENTIAL DATA CLOCK

文件：63.57 Kbytes Page：4 Pages

封装/外壳：28-LCC（J 形引线） 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 6BIT 28PLCC 集成电路（IC） 触发器

封装/外壳：28-LCC（J 形引线） 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 6BIT 28PLCC 集成电路（IC） 触发器

6-BIT REGISTER DIFFERENTIAL DATA CLOCK

文件：63.57 Kbytes Page：4 Pages

6-BIT REGISTER DIFFERENTIAL DATA CLOCK

文件：63.57 Kbytes Page：4 Pages

6-BIT REGISTER DIFFERENTIAL DATA CLOCK

文件：63.57 Kbytes Page：4 Pages

6-BIT REGISTER DIFFERENTIAL DATA CLOCK

文件：63.57 Kbytes Page：4 Pages

6-BIT D REGISTER DIFFERENTIAL DATA AND CLOCK

Description The MC10E/100E451 contains six D−type flip−flops with single−ended outputs and differential data inputs. The common clock input is also differential. The registers are triggered by a positive transition of the positive clock (CLK) input. Features • Differential Inputs: Data and

5V ECL 6?묪it D Register Differential Data and Clock

文件：134.46 Kbytes Page：9 Pages

5V ECL 6?묪it D Register Differential Data and Clock

文件：134.46 Kbytes Page：9 Pages