QUINT DIFFERENTIAL LINE RECEIVER

DESCRIPTION\nThe SY10/100E416 are 5-bit differential line receiving devices. The 2.0GHz of bandwidth provided by the high frequency outputs make the devices ideal for buffering of very high speed oscillators.\nA VBB pin is available to AC couple an input signal to the devices.\nThe design incorporat ■ Differential D and Q\n■ Extended 100E VEE range of –4.2V to –5.5V\n■ VBB output for single-ended use\n■ 600ps max. propagation delay\n■ High frequency outputs\n■ 2 stages of gain\n■ Internal 75KΩ input pull-down resistors\n■ Fully compatible with Motorola 10E/100E416\n■ Available in 28-pin PLCC pa;

QUINT DIFFERENTIAL LINE RECEIVER

文件：62.33 Kbytes Page：4 Pages

QUINT DIFFERENTIAL LINE RECEIVER

DESCRIPTION The SY10/100E416 are 5-bit differential line receiving devices. The 2.0GHz of bandwidth provided by the high frequency outputs make the devices ideal for buffering of very high speed oscillators. A VBB pin is available to AC couple an input signal to the devices. The design incorpor

QUINT DIFFERENTIAL LINE RECEIVER

DESCRIPTION The SY10/100E416 are 5-bit differential line receiving devices. The 2.0GHz of bandwidth provided by the high frequency outputs make the devices ideal for buffering of very high speed oscillators. A VBB pin is available to AC couple an input signal to the devices. The design incorpor

QUINT DIFFERENTIAL LINE RECEIVER

文件：62.33 Kbytes Page：4 Pages

QUINT DIFFERENTIAL LINE RECEIVER

文件：62.33 Kbytes Page：4 Pages

QUINT DIFFERENTIAL LINE RECEIVER

文件：62.33 Kbytes Page：4 Pages

QUINT DIFFERENTIAL LINE RECEIVER

文件：62.33 Kbytes Page：4 Pages

封装/外壳：28-LCC（J 形引线） 包装：散装 描述：IC LINE RCVR QUINT DIFF 28-PLCC 集成电路（IC） 专用逻辑器件

封装/外壳：28-LCC（J 形引线） 包装：管件 描述：IC LINE RCVR QUINT DIFF 28-PLCC 集成电路（IC） 专用逻辑器件

QUINT DIFFERENTIAL LINE RECEIVER

文件：62.33 Kbytes Page：4 Pages

QUINT DIFFERENTIAL LINE RECEIVER

文件：62.33 Kbytes Page：4 Pages

QUINT DIFFERENTIAL LINE RECEIVER

Description The MC10E416/100E416 is a 5-bit differential line receiving device. The 2.0 GHz of bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The design incorporates two stages of gain, internal to the device, making it an ex

5V ECL Quint Differential Line Receiver

文件：132.9 Kbytes Page：9 Pages