Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features  Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and sup

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces

文件：1.21833 Mbytes Page：92 Pages

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces

文件：1.43691 Mbytes Page：96 Pages

STM32 Nucleo-64 boards

Description The STM32 Nucleo board provides an affordable and flexible way for users to try out new concepts and build prototypes with the STM32 microcontroller, choosing from the various combinations of performance, power consumption and features. The Arduino™Uno V3 connectivity support and the

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Description The STM32 Nucleo board provides an affordable and flexible way for users to try out new concepts and build prototypes with the STM32 microcontroller, choosing from the various combinations of performance, power consumption and features. The Arduino™Uno V3 connectivity support and the

STM32 Nucleo-64 boards

Features • Common features – STM32 microcontroller in LQFP64 package – 1 user LED shared with ARDUINO® – 1 user and 1 reset push-buttons – 32.768 kHz crystal oscillator – Board connectors: ◦ ARDUINO® Uno V3 expansion connector ◦ ST morpho extension pin headers for full access to all STM32

Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces

Features ■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz – Single-cycle multiplication and hardware division – Nested interrupt controller with 43 maskable interrupt channels – Interrupt processing (down to 6 CPU cycles) with tail chaining ■ Memories –

MCU

文件：4.30145 Mbytes Page：28 Pages