位置：首页 > IC中文资料第9363页 > SSTUH32866
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
SSTUH32866 | 1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2 RDIMM applications 文件：158 Kbytes Page：28 Pages | Philips 飞利浦 |   | |
SSTUH32866 | 1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2 RDIMM applications | ETC 知名厂家 | ETC | |
1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2 RDIMM applications 文件：158 Kbytes Page：28 Pages | Philips 飞利浦 | | ||
封装/外壳：96-LFBGA 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BUFFER 1.8V 25BIT SOT536 集成电路（IC） 专用逻辑器件 | ETC 知名厂家 | ETC | | |
封装/外壳：96-LFBGA 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BUFFER 1.8V 25BIT SOT536 集成电路（IC） 专用逻辑器件 | ETC 知名厂家 | ETC | | |
1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2 RDIMM applications 文件：158 Kbytes Page：28 Pages | Philips 飞利浦 | | ||
1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2 RDIMM applications 文件：158 Kbytes Page：28 Pages | Philips 飞利浦 | | ||
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Features • 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on C0, C1, and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Drop-in replacement for ICSSS | RENESAS 瑞萨 | | ||
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive | IDT | | ||
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive | IDT | | ||
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Features • 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on C0, C1, and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Drop-in replacement for ICSSS | RENESAS 瑞萨 | | ||
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive | IDT | |
SSTUH32866产品属性
- 类型
描述
- 型号
SSTUH32866
- 制造商
PHILIPS
- 制造商全称
NXP Semiconductors
- 功能描述
1.8 V high output drive 25-bit 1
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
恩XP |
23+ |
LFBGA96 |
3000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
|||
恩XP |
23+ |
96LFBGA (13.5x5.5) |
8000 |
只做原装现货 |
|||
DOMINANT |
23+ |
SMD |
50000 |
全新原装正品现货,支持订货 |
|||
PHI |
24+ |
BGA |
15300 |
公司常备大量原装现货,可开13%增票! |
|||
恩XP |
25+ |
电联咨询 |
7800 |
公司现货,提供拆样技术支持 |
|||
恩XP |
25+ |
96-LFBGA |
9350 |
独立分销商 公司只做原装 诚心经营 免费试样正品保证 |
|||
恩XP |
22+ |
96LFBGA (13.5x5.5) |
9000 |
原厂渠道,现货配单 |
|||
PHI |
22+ |
BGA |
8200 |
原装现货库存.价格优势 |
|||
PHI |
22+ |
BGA |
3000 |
原装正品,支持实单 |
|||
恩XP |
24+ |
96-LFBGA(13.5x5.5) |
56200 |
一级代理/放心采购 |
SSTUH32866规格书下载地址
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2012-11-8
DdatasheetPDF页码索引
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