3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce)

封装/外壳：20-VFBGA 包装：卷带（TR）剪切带（CT） 描述：IC D-TYP LATCH OCT TRI-ST 20-BGA 集成电路（IC） 锁存器

3.3V ABT OCTAL TRANSPARENT D TYPE LATCHES WITH 3 STATE OUTPUTS

文件：449.26 Kbytes Page：18 Pages

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

文件：740.26 Kbytes Page：23 Pages

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

文件：1.07374 Mbytes Page：24 Pages

3.3-V ABT OCTAL TRANSPARENT D-YTPE LATCHES

文件：1.47085 Mbytes Page：26 Pages

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch

文件：342.39 Kbytes Page：13 Pages