10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Operates From 1.65 V to 3.6 V · Inputs Accept Voltages to 5.5 V · Max tpd of 7.3 ns at 3.3 V · Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C · Supports Mixed-Mode Signal Operation on All

10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Operates From 1.65 V to 3.6 V · Inputs Accept Voltages to 5.5 V · Max tpd of 7.3 ns at 3.3 V · Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C · Supports Mixed-Mode Signal Operation on All

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE SNGL 10BIT 24TSSOP 集成电路（IC） 触发器

10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：466.26 Kbytes Page：16 Pages

10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：629.44 Kbytes Page：17 Pages

10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Operates From 1.65 V to 3.6 V · Inputs Accept Voltages to 5.5 V · Max tpd of 7.3 ns at 3.3 V · Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C · Supports Mixed-Mode Signal Operation on All

10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Operates From 1.65 V to 3.6 V · Inputs Accept Voltages to 5.5 V · Max tpd of 7.3 ns at 3.3 V · Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C · Supports Mixed-Mode Signal Operation on All

10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State

DESCRIPTION The 74LVC821A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. This feature allows the use of these devices

10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

General description The 74LVC821A is a high performance, low power, low voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these

10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State

DESCRIPTION The 74LVC821A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. This feature allows the use of these devices