OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

文件：1.05867 Mbytes Page：28 Pages

封装/外壳：20-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC OCT D TRANSP LATCH 3ST 20SO 集成电路（IC） 锁存器

封装/外壳：20-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC OCT TRANSP D-TYP LATCH 20SO 集成电路（IC） 锁存器

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

文件：1.05867 Mbytes Page：28 Pages

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

文件：1.05867 Mbytes Page：28 Pages

Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC573A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

OCTAL TRANSPARENT D-TYPE LATCH WITH 3 STATE OUTPUTS

Description The 74LVC573A provides eight transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to

Low-Voltage CMOS Octal Buffer Flow Through Pinout

Low-Voltage CMOS Octal Transparent Latch With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC573A is a high performance, non−inverting octal transparent latch operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to inp

Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC573A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

OCTAL D-TYPE LATCH HIGH PERFORMANCE

DESCRIPTION The 74LVC573A is a low voltage CMOS OCTAL D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. ■ 5V TOLERANT INPUTS ■ HIGH SPEED: tPD = 6.8ns (MAX.) a