SN74LV595B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, 8-bit Shift Register With 3-State Outputs

1 Features • 2 V to 5.5 V VCC operation • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defense, aerospace, and medical appl

SN74LV595B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, 8-bit Shift Register With 3-State Outputs

1 Features • 2 V to 5.5 V VCC operation • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defense, aerospace, and medical appl

8-bit serial-in/serial-out or parallel-out shift register; 3-state

1. General description The 74LV595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asyn

8-bit serial-in/serial or parallel-out shift register with output latches 3-State

DESCRIPTION The 74LV595 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT595. FEATURES • Optimized for Low Voltage applications: 1.0V to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce)

8-bit serial-in/serial or parallel-out shift register with output latches 3-State

DESCRIPTION The 74LV595 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT595. FEATURES • Optimized for Low Voltage applications: 1.0V to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce)

8-bit serial-in/serial-out or parallel-out shift register; 3-state

1. General description The 74LV595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asyn

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

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