丝印代码：LV14BEP；SN74LV14B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Hex Schmitt-Trigger Inverters

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 14 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defens

丝印代码：LV14BEP；SN74LV14B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Hex Schmitt-Trigger Inverters

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 14 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defens

丝印代码：LV14BEP；SN74LV14B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Hex Schmitt-Trigger Inverters

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 14 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defens

丝印代码：LV14BEP；SN74LV14B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Hex Schmitt-Trigger Inverters

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 14 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defens

Hex inverting Schmitt-trigger

DESCRIPTION The 74LV14 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT14. The 74LV14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. FE

Hex inverting Schmitt-trigger

DESCRIPTION The 74LV14 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT14. The 74LV14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. FE

Hex inverting Schmitt-trigger

DESCRIPTION The 74LV14 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT14. The 74LV14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. FE

Hex inverting Schmitt-trigger

DESCRIPTION The 74LV14 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT14. The 74LV14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. FE

Hex inverting Schmitt-trigger

DESCRIPTION The 74LV14 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT14. The 74LV14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. FE