QUADRUPLE BUS TRANSCEIVERS

1FEATURES · Two-Way Asynchronous Communication Between Data Buses · PNP Inputs Reduce D-C Loading · Hysteresis (Typically 400 mV) at Inputs Improves Noise Margin DESCRIPTION These four-data-line transceivers are designed for asynchronous two-way communications between data buses. SN74LS2

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC TXRX NON-INVERT 5.25V 14SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

QUADRUPLE BUS TRANSCEIVERS

文件：135.01 Kbytes Page：4 Pages

QUADRUPLE BUS TRANSCEIVERS

文件：900.59 Kbytes Page：14 Pages

QUADRUPLE BUS TRANSCEIVERS

1FEATURES · Two-Way Asynchronous Communication Between Data Buses · PNP Inputs Reduce D-C Loading · Hysteresis (Typically 400 mV) at Inputs Improves Noise Margin DESCRIPTION These four-data-line transceivers are designed for asynchronous two-way communications between data buses. SN74LS2

QUADRUPLE BUS TRANSCEIVERS

1FEATURES · Two-Way Asynchronous Communication Between Data Buses · PNP Inputs Reduce D-C Loading · Hysteresis (Typically 400 mV) at Inputs Improves Noise Margin DESCRIPTION These four-data-line transceivers are designed for asynchronous two-way communications between data buses. SN74LS2

QUAD BUS TRANSCEIVER

The SN54/74LS242 and SN54/74LS243 are Quad Bus Transmitters/Receivers designed for 4-line asynchronous 2-way data communications between data buses. • Hysteresis at Inputs to Improve Noise Immunity • 2-Way Asynchronous Data Bus Communication • Input Clamp Diodes Limit High-Speed Termination Eff

QUADRUPLE BUS TRANSCEIVERS

文件：900.59 Kbytes Page：14 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC TXRX NON-INVERT 5.25V 14SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Quadruple Bus Transceiver

General Description This four data line transceiver is designed for asynchronous two-way communications between data buses. It can be used to drive terminated lines down to 133Ω. Features ■ Two-way asynchronous communication between data buses ■ PNP inputs reduce DC loading on bus li

Quadruple Bus Transceiver

General Description This four data line transceiver is designed for asynchronous two-way communications between data buses. It can be used to drive terminated lines down to 133Ω. Features ■ Two-way asynchronous communication between data buses ■ PNP inputs reduce DC loading on bus li

Quadruple Bus Transceiver

General Description This four data line transceiver is designed for asynchronous two-way communications between data buses. It can be used to drive terminated lines down to 133Ω. Features ■ Two-way asynchronous communication between data buses ■ PNP inputs reduce DC loading on bus li

Quadruple Bus Transceiver

General Description This four data line transceiver is designed for asynchronous two-way communications between data buses. It can be used to drive terminated lines down to 133Ω. Features ■ Two-way asynchronous communication between data buses ■ PNP inputs reduce DC loading on bus li

Quadruple Bus Transceivers(with three-state outputs)

● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....)