OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

Operating Voltage Range of 4.5 V to 5.5 V Low Power Consumption, 80-μA Max ICC Typical tpd = 12 ns ±6-mA Output Drive at 5 V Low Input Current of 1 μA Max Inputs Are TTL-Voltage Compatible Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths High-C

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC TXRX NON-INVERT 5.5V 24SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：284.1 Kbytes Page：12 Pages

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：261.66 Kbytes Page：7 Pages

Octal bus transceiver/register; 3-state

GENERAL DESCRIPTION The 74HC/HCT646 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Independent register for A and B buses • Multiplexed real-time and stored data • Output c

Octal bus transceiver/register; 3-state

GENERAL DESCRIPTION The 74HC/HCT646 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Independent register for A and B buses • Multiplexed real-time and stored data • Output c

Octal bus transceiver/register; 3-state

GENERAL DESCRIPTION The 74HC/HCT646 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Independent register for A and B buses • Multiplexed real-time and stored data • Output c

Octal bus transceiver/register; 3-state

GENERAL DESCRIPTION The 74HC/HCT646 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Independent register for A and B buses • Multiplexed real-time and stored data • Output c

Octal bus transceiver/register; 3-state

GENERAL DESCRIPTION The 74HC/HCT646 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Independent register for A and B buses • Multiplexed real-time and stored data • Output c