Dual 2-Line To 4-Line Decoders/Demultiplexers

1 Features • Operating voltage range of 4.5 V to 5.5 V • Outputs can drive up to 10 LSTTL loads • Low power consumption, 80-μA max ICC • Typical tpd = 10 ns • ±4-mA output drive at 5 V • Low input current of 1 μA max • Inputs are TTL-voltage compatible • Designed specifically for high-spee

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1X2:4 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

文件：299.13 Kbytes Page：11 Pages

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

文件：705.3 Kbytes Page：15 Pages

Dual 2-Line To 4-Line Decoders/Demultiplexers

1 Features • Operating voltage range of 4.5 V to 5.5 V • Outputs can drive up to 10 LSTTL loads • Low power consumption, 80-μA max ICC • Typical tpd = 10 ns • ±4-mA output drive at 5 V • Low input current of 1 μA max • Inputs are TTL-voltage compatible • Designed specifically for high-spee

Dual 2-Line To 4-Line Decoders/Demultiplexers

1 Features • Operating voltage range of 4.5 V to 5.5 V • Outputs can drive up to 10 LSTTL loads • Low power consumption, 80-μA max ICC • Typical tpd = 10 ns • ±4-mA output drive at 5 V • Low input current of 1 μA max • Inputs are TTL-voltage compatible • Designed specifically for high-spee

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

文件：705.3 Kbytes Page：15 Pages

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

文件：299.13 Kbytes Page：11 Pages

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

文件：705.3 Kbytes Page：15 Pages

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-

Dual 2-to-4 line decoder/demultiplexer