High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

Features • Synchronous Programmable ÷N Counter N = 3 to 9999 or 15999 • Presettable Down-Counter • Fully Static Operation • Mode-Select Control of Initial Decade Counting Function (÷10, 8, 5, 4, 2) • Master Preset Initialization • Latchable ÷N Output • Fanout (Over Temperature Range) - S

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

Features • Synchronous Programmable ÷N Counter N = 3 to 9999 or 15999 • Presettable Down-Counter • Fully Static Operation • Mode-Select Control of Initial Decade Counting Function (÷10, 8, 5, 4, 2) • Master Preset Initialization • Latchable ÷N Output • Fanout (Over Temperature Range) - S

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

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High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：381.72 Kbytes Page：14 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：352.13 Kbytes Page：14 Pages