SNx4HC259 8-Bit Addressable Latches

1 Features • Wide operating voltage range of 2 V to 6 V • High-current inverting outputs drive up to 10 LSTTL loads • Low power consumption, 80-μA max ICC • Typical tpd = 14 ns • ±4-mA output drive at 5 V • Low input current of 1 μA max • 8-bit parallel-out storage register performs serial

8-BIT ADDRESSABLE LATCHES

文件：519.789 Kbytes Page：16 Pages

SNx4HC259 8-Bit Addressable Latches

1 Features • Wide operating voltage range of 2 V to 6 V • High-current inverting outputs drive up to 10 LSTTL loads • Low power consumption, 80-μA max ICC • Typical tpd = 14 ns • ±4-mA output drive at 5 V • Low input current of 1 μA max • 8-bit parallel-out storage register performs serial

封装/外壳：16-SOIC（0.209"，5.30mm 宽） 包装：管件 描述：IC ADDRESSABLE LATCH 8BIT 16SO 集成电路（IC） 锁存器

8-BIT ADDRESSABLE LATCHES

文件：1.10892 Mbytes Page：21 Pages

8-BIT ADDRESSABLE LATCHES

文件：519.789 Kbytes Page：16 Pages

8-BIT ADDRESSABLE LATCHES

文件：365.22 Kbytes Page：15 Pages

8-BIT ADDRESSABLE LATCHES

文件：686.56 Kbytes Page：19 Pages

8-BIT ADDRESSABLE LATCHES

文件：686.56 Kbytes Page：19 Pages

8-BIT ADDRESSABLE LATCHES

文件：686.56 Kbytes Page：19 Pages

8-bit addressable latch

8-bit addressable latch

GENERAL DESCRIPTION The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Outp

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l

8-bit addressable latch