8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：636.54 Kbytes Page：19 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：1.76803 Mbytes Page：34 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：并行或串行至串行 包装：卷带（TR） 描述：IC SHIFT REGISTER 8BIT 16-SOIC 集成电路（IC） 移位寄存器

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：1.76803 Mbytes Page：34 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：636.54 Kbytes Page：19 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：1.76803 Mbytes Page：34 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：636.54 Kbytes Page：19 Pages

8-bit parallel-in/serial-out shift register

GENERAL DESCRIPTION The 74HC/HCT166 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT166 are 8-bit shift registers which have a fully synchronous serial or parallel data entry

8-bit parallel-in/serial out shift register

1. General description The 74HC166; 74HCT166 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded in

8-bit parallel-in/serial-out shift register

GENERAL DESCRIPTION The 74HC/HCT166 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT166 are 8-bit shift registers which have a fully synchronous serial or parallel data entry

CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • 8-Bit Shift Register (P-IN, S-OUT) General The 74HC166D is a high speed CMOS 8-BIT PARALLEL/SERIAL-IN, SERIAL-OUT SHIFT REGISTER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS

8-bit parallel-in/serial out shift register

1. General description The 74HC166; 74HCT166 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded in