8-LINE TO 3-LINE PRIORITY ENCODERS

文件：585.48 Kbytes Page：17 Pages

8-LINE TO 3-LINE PRIORITY ENCODERS

文件：1.07208 Mbytes Page：19 Pages

8-LINE TO 3-LINE PRIORITY ENCODERS

文件：1.07208 Mbytes Page：19 Pages

8-LINE TO 3-LINE PRIORITY ENCODERS

文件：585.48 Kbytes Page：17 Pages

8-LINE TO 3-LINE PRIORITY ENCODERS

文件：585.48 Kbytes Page：17 Pages

封装/外壳：16-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC PRIORITY ENCOD 1 X 8:3 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

封装/外壳：16-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC PRIORITY ENCOD 1 X 8:3 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

8 TO 3 LINE PRIORITY ENCODER

The M54/74HC148 is a high speed CMOS 8-TO-3 LINE PRIORITY ENCODER fabricated in silicon gate C2 MOS technology. It has the same high speed performance for LSTTL combined with true CMOS low power consumption. The M54/74HC148 encodes eight data lines to three-line (4-2-1) binary (octal). Casca

8-3 Line Priority Encoder

The MM74HC148 priority encoder utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low power consumption typical of CMOS circuits, as well as the speeds and output drive similar to LB-TTL. 1. Typical propagation delay: 13 ns 2. Wide supply voltage r

8-to-3-line Octal Priority Encoder

Description The HD74HC148 encodes eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) is provided to allow octal expansion without the need for external circuitry.The data inputs and outputs are active at the low logic level. Fe

8-to-3-line Octal Priority Encoder

Description The HD74HC148 encodes eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) is provided to allow octal expansion without the need for external circuitry.The data inputs and outputs are active at the low logic level. Fe

8-TO-3 LINE PRIORITY ENCODER

文件：207.96 Kbytes Page：4 Pages