DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

文件：535.95 Kbytes Page：16 Pages

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

文件：678.89 Kbytes Page：18 Pages

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

文件：540.37 Kbytes Page：16 Pages

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

文件：914.1 Kbytes Page：22 Pages

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS139.

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

High Speed CMOS Logic

文件：641.19 Kbytes Page：6 Pages

High Speed CMOS Logic

文件：696.19 Kbytes Page：6 Pages