HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE

文件：201.65 Kbytes Page：7 Pages

HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE

文件：201.65 Kbytes Page：7 Pages

Parallel D-Type Register with Enable

General Description The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. Features ■ 6-bit high-speed parallel register ■ Positive edge-triggered D-type inputs ■ Fully buffered common clock

Hex D flip-flop with enable

DESCRIPTION The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge-triggered. The state of each D input, one setup time befor

Parallel D-Type Register with Enable

General Description The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. Features ■ 6-bit high-speed parallel register ■ Positive edge-triggered D-type inputs ■ Fully buffered common clock

Parallel D Register with Enable

文件：166.93 Kbytes Page：8 Pages

Parallel D Register with Enable

文件：166.93 Kbytes Page：8 Pages