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SN74F112NSR价格
参考价格：￥1.7318
型号：SN74F112NSR 品牌：TI 备注：这里有SN74F112NSR多少钱，2026年最近7天走势，今日出价，今日竞价，SN74F112NSR批发/采购报价，SN74F112NSR行情走势销售排行榜，SN74F112NSR报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
SN74F112NSR | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t | TI 德州仪器 |   | |
SN74F112NSR | 封装/外壳：16-SOIC（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 16SO 集成电路（IC） 触发器 | TI 德州仪器 | | |
SN74F112NSR | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP 文件：627.07 Kbytes Page：13 Pages | TI 德州仪器 | | |
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t | TI 德州仪器 | | ||
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP 文件：627.07 Kbytes Page：13 Pages | TI 德州仪器 | | ||
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP 文件：627.07 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K negative edge-triggered flip-flop DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level | Philips 飞利浦 | | ||
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J | Fairchild 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J | Fairchild 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | Fairchild 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | Fairchild 仙童半导体 | |
SN74F112NSR产品属性
- 类型
描述
- 型号
SN74F112NSR
- 功能描述
触发器 Dual Neg-Edge-Trig J-K Flip-Flop
- RoHS
否
- 制造商
Texas Instruments
- 电路数量
2
- 逻辑系列
SN74
- 逻辑类型
D-Type Flip-Flop
- 极性
Inverting, Non-Inverting
- 输入类型
CMOS
- 传播延迟时间
4.4 ns
- 高电平输出电流
- 16 mA
- 低电平输出电流
16 mA
- 电源电压-最大
5.5 V
- 最大工作温度
+ 85 C
- 安装风格
SMD/SMT
- 封装/箱体
X2SON-8
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
25+ |
SO-16 |
21000 |
正规渠道,免费送样。支持账期,BOM一站式配齐 |
|||
TI/德州仪器 |
24+ |
NA/ |
713 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
|||
TI |
SOP-0.52 |
68500 |
一级代理 原装正品假一罚十价格优势长期供货 |
||||
TI |
23+ |
NA |
20000 |
||||
TI/德州仪器 |
23+ |
SOP |
3200 |
正规渠道,只有原装! |
|||
TI |
24+ |
SOP-16 |
122 |
只做原装，欢迎询价，量大价优 |
|||
TI/德州仪器 |
23+ |
SOP |
5000 |
全新原装,支持实单,非诚勿扰 |
|||
TI |
24+ |
SMD |
3000 |
自己现货 |
|||
TI/德州仪器 |
25+ |
原厂封装 |
9999 |
||||
TI |
24+ |
con |
10000 |
查现货到京北通宇商城 |
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SN74F112NSR规格书下载地址
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