型号 功能描述 生产厂家 企业 LOGO 操作

Positive J-K positive edge-triggered flip-flops

DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are

Philips

飞利浦

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

Fairchild

仙童半导体

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

Fairchild

仙童半导体

Dual JK Positive Edge-Triggered Flip-Flop

文件:80.64 Kbytes Page:7 Pages

Fairchild

仙童半导体

Dual JK Positive Edge-Triggered Flip-Flop

文件:133.12 Kbytes Page:10 Pages

NSC

国半

更新时间:2025-11-2 11:12:01
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
FAIRCHI
24+
SOIC-16
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2447
DIP
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TI/德州仪器
23+
50000
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TI
2019
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454
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FAIR
24+
16SOIC
4000
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24+
5000
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NS
24+
LCC
1025
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恩XP
21+
SOP16
1500
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FAIRCHILD
24+
SOIC-16
25000
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MOT
24+
SOP
17500
公司常备大量原装正品现货!量大价优!

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