18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · DOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation · Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V

18-bit registered driver with inverted register enable 3-State

DESCRIPTION The 74AVC16834 is a 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance state

18-bit registered driver with inverted register enable and Dynamic Controlled Outputs (3-State)

DESCRIPTION The 74AVC16834A is a 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance stat

18-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state

1. General description The 74AVC16834A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-

18-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state

1. General description The 74AVC16834A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-

18-bit registered driver with inverted register enable and Dynamic Controlled Outputs (3-State)

DESCRIPTION The 74AVC16834A is a 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance stat