LOW-POWER DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

1FEATURES • Available in the Texas Instruments NanoStar™ Package • Low Static-Power Consumption (ICC = 0.9 mA Maximum) • Low Dynamic-Power Consumption (Cpd = 4.3 pF Typ at 3.3 V) • Low Input Capacitance (Ci = 1.5 pF Typical) • Low Noise – Overshoot and Undershoot

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition

Low-power dual D-type flip-flop; positive-edge trigger

文件：94.62 Kbytes Page：18 Pages

Low-power dual D-type flip-flop; positive-edge trigger

Low-power dual D-type flip-flop; positive-edge trigger

Low-power dual D-type flip-flop; positive-edge trigger

文件：94.62 Kbytes Page：18 Pages