LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

1FEATURES 2• Available in the Texas Instruments NanoStar™ Package • Low Static-Power Consumption (ICC = 0.9 μA Maximum) • Low Dynamic-Power Consumption (Cpd = 3 pF Typ at 3.3 V) • Low Input Capacitance (Ci = 1.5 pF Typical) • Low Noise – Overshoot and Undershoot

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock

Low-power dual D-type flip-flop; positive-edge trigger

Low-power dual D-type flip-flop; positive-edge trigger

Low-power dual D-type flip-flop; positive-edge trigger