LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

1FEATURES 2• Available in the Texas Instruments NanoStar™ Package • Low Static-Power Consumption (ICC = 0.9 μA Maximum) • Low Dynamic-Power Consumption (Cpd = 3 pF Typ at 3.3 V) • Low Input Capacitance (Ci = 1.5 pF Typical) • Low Noise – Overshoot and Undershoot

封装/外壳：8-VFSOP（0.091"，2.30mm 宽） 功能：标准 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 8VSSOP 集成电路（IC） 触发器

LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

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LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

1FEATURES 2• Available in the Texas Instruments NanoStar™ Package • Low Static-Power Consumption (ICC = 0.9 μA Maximum) • Low Dynamic-Power Consumption (Cpd = 3 pF Typ at 3.3 V) • Low Input Capacitance (Ci = 1.5 pF Typical) • Low Noise – Overshoot and Undershoot

LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

1FEATURES 2• Available in the Texas Instruments NanoStar™ Package • Low Static-Power Consumption (ICC = 0.9 μA Maximum) • Low Dynamic-Power Consumption (Cpd = 3 pF Typ at 3.3 V) • Low Input Capacitance (Ci = 1.5 pF Typical) • Low Noise – Overshoot and Undershoot

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock

Low-power dual D-type flip-flop; positive-edge trigger

Low-power dual D-type flip-flop; positive-edge trigger

Low-power dual D-type flip-flop; positive-edge trigger