18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process · UBT™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes · ESD Protection Exceeds 2000

封装/外壳：56-BSSOP（0.295"，7.50mm 宽） 包装：管件 描述：IC UNIV BUS TXRX 18BIT 56SSOP 集成电路（IC） 通用总线功能

18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process · UBT™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes · ESD Protection Exceeds 2000

18-bit universal bus transceiver 3-State

DESCRIPTION The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. FEATURES • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • Direct in

18-bit universal bus transceiver; 3-state

1 General description The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latc

18-bit universal bus transceiver; 3-state

1 General description The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latc

18-bit universal bus transceiver 3-State

DESCRIPTION The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. FEATURES • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • Direct in

18-bit Universal Bus Transceivers with 3-state Outputs

Description Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held a