16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 to 3.6 V · Max tpd of 4.2 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors · Latch-Up Performance Exceeds 250 mA Per JESD 17 · ES

具有三态输出的 16 位边沿 D 类触发器

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：318.27 Kbytes Page：14 Pages

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 to 3.6 V · Max tpd of 4.2 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors · Latch-Up Performance Exceeds 250 mA Per JESD 17 · ES

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 to 3.6 V · Max tpd of 4.2 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors · Latch-Up Performance Exceeds 250 mA Per JESD 17 · ES

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 to 3.6 V · Max tpd of 4.2 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors · Latch-Up Performance Exceeds 250 mA Per JESD 17 · ES

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 to 3.6 V · Max tpd of 4.2 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors · Latch-Up Performance Exceeds 250 mA Per JESD 17 · ES

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 to 3.6 V · Max tpd of 4.2 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors · Latch-Up Performance Exceeds 250 mA Per JESD 17 · ES

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 to 3.6 V · Max tpd of 4.2 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors · Latch-Up Performance Exceeds 250 mA Per JESD 17 · ES

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 to 3.6 V · Max tpd of 4.2 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors · Latch-Up Performance Exceeds 250 mA Per JESD 17 · ES

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 to 3.6 V · Max tpd of 4.2 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors · Latch-Up Performance Exceeds 250 mA Per JESD 17 · ES

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 to 3.6 V · Max tpd of 4.2 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors · Latch-Up Performance Exceeds 250 mA Per JESD 17 · ES

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：318.27 Kbytes Page：14 Pages

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：318.27 Kbytes Page：14 Pages

封装/外壳：48-TFSOP（0.173"，4.40mm 宽） 功能：标准 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 8BIT 48TVSOP 集成电路（IC） 触发器

封装/外壳：48-BSSOP（0.295"，7.50mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE DUAL 8BIT 48SSOP 集成电路（IC） 触发器

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：318.27 Kbytes Page：14 Pages

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：318.27 Kbytes Page：14 Pages

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：318.27 Kbytes Page：14 Pages

2.5V/3.3V 16-bit edge-triggered D-type flip-flop 3-State

DESCRIPTION The 74ALVCH16374 is a 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. Th

Low Voltage 16-Bit D-Type Flip-Flop with Bushold

General Description The ALVCH16374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 16-bit o

LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS

DESCRIPTION The 74ALVCH16374 is a low voltage CMOS 16 BIT D-TYPE FLIP-FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and five-layer metal wiring C2MOS technology. It is ideal for low power and very high speed 1.65 to 3.6V applications; it can be interfaced to 3.6V

2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

1. General description The 74ALVCH16374 is a 16-bit edge-triggered D-type flip-flop with bus hold inputs and 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlli