20-bit buffer/line driver, non-inverting,with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVCH162827 high-performance CMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 12 mA at 3.0

20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state

1 General description The 74ALVCH162827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NAND output enables (nOE1 and nOE2) for maximum control flexibility. The 74ALVCH162827 is designed with 30 Ω series resisters

20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state

1 General description The 74ALVCH162827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NAND output enables (nOE1 and nOE2) for maximum control flexibility. The 74ALVCH162827 is designed with 30 Ω series resisters

20-bit buffer/line driver, non-inverting,with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVCH162827 high-performance CMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 12 mA at 3.0

20-bit Buffers / Drivers with 3-state Outputs

Description The HD74ALVCH162827 is composed of two 10-bit sections with separate output enable signals. For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either output enable input is h