18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 V to 3.6 V · Max tpd of 2 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Ideal for Use in PC100 Register DIMM, Revision 1.1 · Latch-Up Performance Exceeds 250 mA Per JESD 17 · ESD Protection Exceeds JESD 22 -

封装/外壳：56-VFBGA 包装：管件 描述：IC UNIV BUS DVR 18BIT 56BGA 集成电路（IC） 通用总线功能

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

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Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs

General Description The ALVC16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.The 74ALVC16835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74A

18-bit registered driver; 3-state

1 General description The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is la

18-bit registered driver 3-State

DESCRIPTION The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on

18-bit registered driver 3-State

DESCRIPTION The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on

18-bit registered driver; 3-state

1 General description The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is la