QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

FEATURES · Operates from 1.65 V to 3.6 V · Max tpd of 2.8 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Latch-up Performance Exceeds 250 mA Per JESD 17 · ESD Performance Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)

Quad buffer/line driver; 3-state

DESCRIPTION The 74ALVC125 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. FEATURES • Wide supply voltage range fr

Quad buffer/line driver; 3-state

1. General description The 74ALVC125 is a quad non-inverting buffer/line driver with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH on the nOE pin causes the outputs to assume a high-impedance OFF-state. 2. Features and benefits • Wide supply

Quad buffer/line driver; 3-state

1. General description The 74ALVC125 is a quad non-inverting buffer/line driver with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH on the nOE pin causes the outputs to assume a high-impedance OFF-state. 2. Features and benefits • Wide supply

Quad buffer/line driver; 3-state

Quad buffer/line driver; 3-state