OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

Bus Transceivers/Registers Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Choice of True or Inverting Data Paths Choice of 3-State or Open-Collector Outputs to A Bus description These devices consist of bus-transceiver circuits, D-type flip-flo

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC TXRX INVERT 5.5V 24SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：906.08 Kbytes Page：33 Pages

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：700.98 Kbytes Page：33 Pages

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC TXRX INVERT 5.5V 24SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：331.92 Kbytes Page：22 Pages

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：700.98 Kbytes Page：33 Pages

Transceiver/register

DESCRIPTION The 74LAS651 and 74ALS652 transceivers/registers consist of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clock

Transceiver/register

DESCRIPTION The 74LAS651 and 74ALS652 transceivers/registers consist of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clock

Transceiver/register

DESCRIPTION The 74LAS651 and 74ALS652 transceivers/registers consist of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clock