7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 20 ns at 5 V 3-State Outputs Directly Drive Bus Lines Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise ESD Protection Exceeds JESD 22 − 2000-V Hu

IEEE 1284 Transceiver

General Description The 74ACT1284 contains four non-inverting bidirectional buffers and three non-inverting buffers with open Drain outputs and high drive capability on the B Ports. It is intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabil

IEEE 1284 Transceiver

General Description The 74ACT1284 contains four non-inverting bidirectional buffers and three non-inverting buffers with open Drain outputs and high drive capability on the B Ports. It is intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabil

IEEE 1284 Transceiver

General Description The 74ACT1284 contains four non-inverting bidirectional buffers and three non-inverting buffers with open Drain outputs and high drive capability on the B Ports. It is intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabil

HIGH SPEED IEEE1284 TRANSCEIVER

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IEEE 1284 Transceiver

文件：265.88 Kbytes Page：7 Pages