10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

10-bit bus interface latch; 3-state

10-bit bus interface latch 3-State

DESCRIPTION The 74ABT841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity • Ideal where high speed, lig

10-bit bus interface latch; 3-state

10-bit bus interface latch 3-State

DESCRIPTION The 74ABT841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity • Ideal where high speed, lig

10-bit bus interface latch 3-State

DESCRIPTION The 74ABT841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity • Ideal where high speed, lig