9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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封装/外壳：24-SOIC（0.295"，7.50mm 宽） 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 9BIT 20SOIC 集成电路（IC） 触发器

9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

9-bit D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT823 Bus interface Register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel registers with positive edge-triggered D-type

9-bit D-type flip-flop with reset and enable; 3-state

9-bit D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT823 Bus interface Register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel registers with positive edge-triggered D-type

9-bit D-type flip-flop with reset and enable; 3-state

9-bit D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT823 Bus interface Register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel registers with positive edge-triggered D-type