DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’” Packages, Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The ‘73, and 'H73, contain two independent JK flip-flops with individual J-K, clock, and direct clear inputs. The ‘

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：872.08 Kbytes Page：17 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes Page：13 Pages

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

具有清零端和三态输出的双路 J-K 触发器

丝印代码：SN54LS73AJ；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’” Packages, Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The ‘73, and 'H73, contain two independent JK flip-flops with individual J-K, clock, and direct clear inputs. The ‘

丝印代码：SN54LS73AJ；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’” Packages, Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The ‘73, and 'H73, contain two independent JK flip-flops with individual J-K, clock, and direct clear inputs. The ‘

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes Page：13 Pages

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：872.08 Kbytes Page：17 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：872.08 Kbytes Page：17 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes Page：13 Pages

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the