9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

The SN54/74LS280 is a Universal 9-Bit Parity Generator/Checker. It features odd/even outputs to facilitate either odd or even parity. By cascading, the word length is easily expanded. The LS280 is designed without the expander input implementation, but the corresponding function is provided by an

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Can Be Used to Upgrade Existing Systems using MSI Parity Circuits Typical Data-to-Output Delay of Only 14 ns for “S280 and 33 ns for ‘LS280 Typical Power Dissipation: ‘LS280. ..80 mW ‘S280. . . 335 mW descrip

9 位奇/偶校验发生器/检测器

These universal, monolithic, nine-bit parity generators/checkers utilize Schottky-clamped TTL high-performance circuitry and feature odd/even outputs to facilitate operation of either odd or even parity application. The word-length capability is easily expanded by cascading as shown under typical ap • Generates Either Odd or Even Parity for Nine Data Lines• Cascadable for n-Bits• Can Be Used to Upgrade Existing Systems using MSI Parity Circuits• Typical Data-to-Output Delay of Only 14 ns for 'S280 and 33 ns for 'LS280• Typical Power Dissipation:• 'LS280 … 80 mW• 'S280 … 335 mW   logic symbol;

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：901.09 Kbytes Page：17 Pages

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：227.77 Kbytes Page：6 Pages

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：899.48 Kbytes Page：24 Pages

丝印代码：SN54LS280J；9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Can Be Used to Upgrade Existing Systems using MSI Parity Circuits Typical Data-to-Output Delay of Only 14 ns for “S280 and 33 ns for ‘LS280 Typical Power Dissipation: ‘LS280. ..80 mW ‘S280. . . 335 mW descrip

丝印代码：SN54LS280J；9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Can Be Used to Upgrade Existing Systems using MSI Parity Circuits Typical Data-to-Output Delay of Only 14 ns for “S280 and 33 ns for ‘LS280 Typical Power Dissipation: ‘LS280. ..80 mW ‘S280. . . 335 mW descrip

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

The SN54/74LS280 is a Universal 9-Bit Parity Generator/Checker. It features odd/even outputs to facilitate either odd or even parity. By cascading, the word length is easily expanded. The LS280 is designed without the expander input implementation, but the corresponding function is provided by an

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：899.48 Kbytes Page：24 Pages

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：901.09 Kbytes Page：17 Pages

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：227.77 Kbytes Page：6 Pages

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：227.77 Kbytes Page：6 Pages

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：899.48 Kbytes Page：24 Pages

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：901.09 Kbytes Page：17 Pages

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：227.77 Kbytes Page：6 Pages