军用 3 通道、3 输入、4.5V 至 5.5V 双极或非门

These devices contain three independent 3-input NOR gates. The SN5427 and SN54LS27 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7427 and SN74LS27 are characterized for operation from 0°C to 70°C.   • Package Options Include Plastic “Small Outline\" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs\n• Dependable Texas Instruments Quality and Reliability;

TRIPLE 3-INPUT NOR GATE

TRIPLE 3-INPUT POSITVE-NOR GATES

文件：913.52 Kbytes Page：18 Pages

TRIPLE 3-INPUT NOR GATE

文件：122.13 Kbytes Page：4 Pages

TRIPLE 3-INPUT POSITIVE-NOR GATES

文件：223.93 Kbytes Page：8 Pages

OCTAL D FLIP-FLOP WITH CLEAR

The SN54/74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing. • 8-Bit High Speed Register • Parallel Register • Commo

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

• Contains Eight Flip-Flops With Single-Rail Outputs • Buffered Clock and Direct Clear Inputs • Individual Data Input to Each Flip-Flop • Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators description These monolithic, positive-edge-triggered flipflops ut

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

• Contains Eight Flip-Flops With Single-Rail Outputs • Buffered Clock and Direct Clear Inputs • Individual Data Input to Each Flip-Flop • Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators description These monolithic, positive-edge-triggered flipflops ut

OCTAL D FLIP-FLOP WITH CLEAR

The SN54/74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing. • 8-Bit High Speed Register • Parallel Register • Commo

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

• Contains Eight Flip-Flops With Single-Rail Outputs • Buffered Clock and Direct Clear Inputs • Individual Data Input to Each Flip-Flop • Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators description These monolithic, positive-edge-triggered flipflops ut

QUAD SET-RESET LATCH

QUAD SET-RESET LATCH LOW POWER SCHOTTKY

QUAD SET-RESET LATCH

QUAD SET-RESET LATCH LOW POWER SCHOTTKY

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

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OCTAL D FLIP-FLOP WITH CLEAR

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

文件：643.97 Kbytes Page：8 Pages

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

文件：641.59 Kbytes Page：8 Pages

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

文件：95.86 Kbytes Page：6 Pages

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

文件：643.97 Kbytes Page：8 Pages

4 BIT BY 4 BIT BINARY MULTIPLER WITH 3-STATE OUTPUTS

文件：362.34 Kbytes Page：10 Pages

QUADRUPLE S-R LATCHES

文件：892.4 Kbytes Page：18 Pages

QUADRUPLE S-R LATCHES

文件：162.87 Kbytes Page：5 Pages

QUADRUPLE S-R LATCHES

文件：162.87 Kbytes Page：5 Pages

QUADRUPLE S-R LATCHES

文件：892.4 Kbytes Page：18 Pages

QUADRUPLE S-R LATCHES

文件：892.4 Kbytes Page：18 Pages

QUADRUPLE S-R LATCHES

文件：162.87 Kbytes Page：5 Pages

QUADRUPLE S-R LATCHES

文件：162.87 Kbytes Page：5 Pages

QUADRUPLE S-R LATCHES

文件：892.4 Kbytes Page：18 Pages

TRIPLE 3-INPUT POSITIVE-NOR GATES

文件：223.93 Kbytes Page：8 Pages

TRIPLE 3-INPUT POSITIVE-NOR GATES

文件：223.93 Kbytes Page：8 Pages

TRIPLE 3-INPUT NOR GATE

文件：122.13 Kbytes Page：4 Pages

TRIPLE 3-INPUT POSITIVE NOR GATES

文件：897.12 Kbytes Page：18 Pages

TRIPLE 3-INPUT POSITVE-NOR GATES

文件：913.52 Kbytes Page：18 Pages

DUAL J.K POSITVE.EDGE.TRIGGERED FLIP.FLOPS WITH PRESET AND CLEAR

文件：579.2 Kbytes Page：12 Pages

TRIPLE 3-INPUT POSITIVE-NOR GATES

文件：223.93 Kbytes Page：8 Pages

TRIPLE 3-INPUT POSITIVE-NOR GATES

文件：223.93 Kbytes Page：8 Pages