SNx4HC166 8-Bit Parallel-Load Shift Registers

1 Features • Wide operating voltage range of 2 V to 6 V • Outputs can drive up to 10 LSTTL loads • Low power consumption, 80-μA max ICC • Typical tpd = 13 ns • ±4-mA output drive at 5 V • Low input current of 1 μA max • Synchronous load • Direct overriding clear • Parallel-to-serial conve

并联负载 8 位移位寄存器

These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR)\\ input. The parallel-in or serial-in modes are established by the shift/load (SH/LD)\\ input. When high, SH/LD\\ enables the serial (SER) data input and couples the eight fli • Wide Operating Voltage Range of 2 V to 6 V\n• Outputs Can Drive Up To 10 LSTTL Loads\n• Low Power Consumption, 80-µA Max ICC\n• Typical tpd = 13 ns\n• ±4-mA Output Drive at 5 V\n• Low Input Current of 1 µA Max\n• Synchronous Load\n• Direct Overriding Clear\n• Parallel-to-Serial Conversion;

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：1.76803 Mbytes Page：34 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：134.77 Kbytes Page：9 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：636.54 Kbytes Page：19 Pages

丝印代码：SN54HC166J；SNx4HC166 8-Bit Parallel-Load Shift Registers

1 Features • Wide operating voltage range of 2 V to 6 V • Outputs can drive up to 10 LSTTL loads • Low power consumption, 80-μA max ICC • Typical tpd = 13 ns • ±4-mA output drive at 5 V • Low input current of 1 μA max • Synchronous load • Direct overriding clear • Parallel-to-serial conve

SNx4HC166 8-Bit Parallel-Load Shift Registers

1 Features • Wide operating voltage range of 2 V to 6 V • Outputs can drive up to 10 LSTTL loads • Low power consumption, 80-μA max ICC • Typical tpd = 13 ns • ±4-mA output drive at 5 V • Low input current of 1 μA max • Synchronous load • Direct overriding clear • Parallel-to-serial conve

并联负载 8 位移位寄存器

These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR)\\ input. The parallel-in or serial-in modes are established by the shift/load (SH/LD)\\ input. When high, SH/LD\\ enables the serial (SER) data input and couples the eight fli • Wide Operating Voltage Range of 2 V to 6 V\n• Outputs Can Drive Up To 10 LSTTL Loads\n• Low Power Consumption, 80-µA Max ICC\n• Typical tpd = 13 ns\n• ±4-mA Output Drive at 5 V\n• Low Input Current of 1 µA Max\n• Synchronous Load\n• Direct Overriding Clear\n• Parallel-to-Serial Conversion;

SNx4HC166 8-Bit Parallel-Load Shift Registers

1 Features • Wide operating voltage range of 2 V to 6 V • Outputs can drive up to 10 LSTTL loads • Low power consumption, 80-μA max ICC • Typical tpd = 13 ns • ±4-mA output drive at 5 V • Low input current of 1 μA max • Synchronous load • Direct overriding clear • Parallel-to-serial conve

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：636.54 Kbytes Page：19 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：1.76803 Mbytes Page：34 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：134.77 Kbytes Page：9 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：636.54 Kbytes Page：19 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：1.76803 Mbytes Page：34 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：134.77 Kbytes Page：9 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：1.76803 Mbytes Page：34 Pages

8-BIT PARALLEL-LOAD SHIFT REGISTERS

文件：134.77 Kbytes Page：9 Pages

High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register

文件：274.45 Kbytes Page：13 Pages