Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)

Description The SL2305 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and rec

Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer

Description The SL2305 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and rec

封装/外壳：8-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC BUFFER 140MHZ 5CH 3.3V 8TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer

Description The SL2305 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and rec

Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)

Description The SL2305 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and rec

Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)

Description The SL2305 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and rec

Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer

Description The SL2305 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and rec