Jitter Attenuator Clock Multiplier

The Si5317C jitter attenuator combines third-generation DSPLL technology to enable any-frequency clock generation and jitter attenuation for applications requiring a high level of jitter performance. This device supports 1 input(s), 2 output(s) and has a maximum frequency output of 200 MHz. The Si53

PIN-CONTROLLED 1–711 MHZ JITTER CLEANING CLOCK

Features  Provides jitter attenuation for any clock frequency  One clock input / two clock outputs  Input/output frequency range: 1–711 MHz  Ultra low jitter: 300 fs (12 kHz–20 MHz) typical  Simple pin control interface  Selectable loop bandwidth for jitter attenuation: 60 Hz–8.4 k

Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Description The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications that require jitter attenuation without clock multiplication. The Si5317 accepts a single clock input ranging from 1 to 710 MHz and generates two low jitter clock outputs at the same frequency. The cl

封装/外壳：36-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK JITTER CLEANR PROG 36QFN 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：36-VFQFN 裸露焊盘 包装：卷带（TR） 描述：IC CLK JITTER CLEANR PROG 36QFN 集成电路（IC） 时钟发生器，PLL，频率合成器

2.5 V to 5.5 V, 230uA, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs

GENERAL DESCRIPTION The AD5332/AD5333/AD5342/AD5343 are dual 8-, 10-, and 12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 230 µA at 3 V, and feature a power-down pin, PD that further reduces the current to 80 nA. These devices incorporate an on-chip output buffer that can dr

Variable Divided Voltage Generator for LCD Use?

Overview The LA5317M is a variable divided voltage generator IC for multiple drive of LCD matrix. Features • Power supply for variable bias LCD drive (1/5 to 1/20 bias available by on-chip resistances). • 5 operational amplifiers to deliver 5 voltage outputs. • Low current drain (1.6mA typ).

Single Phase Bridge Rectifier 8 Amp

Features: ● Low Forward Voltage Drop ● Surge Overload Rating: 200A (Peak) ● Mounting Hole Thru for #6 Screw

SONET/SDH Payload Extractor/Aligner for 9953 Mbit/s

FEATURES • Monolithic single channel STS-192/STM-64 or quad channel STS-48/STM-16 SONET/SDH Payload extractor/aligner. • Designed for use in interface applications operating at serial interface speeds of up to OC-192 rates: • single STS-192c (STM-64/ AU4-64c); • single STS-192 (STM-64/AU

2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs

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