1.25MHz, 1.5A Step-Down Switching Regulator

Description The SC4517A is a current mode switching regulator with an integrated switch, operating at 1.25MHz with separate sync & enable functions. The integrated switch allows for cost effective low power solutions (peak switch current 1.5 amps). The sync function allows customers to synchr

封装/外壳：8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 功能：降压 包装：卷带（TR） 描述：IC REG BUCK ADJ 1.5A 8MSOP 集成电路（IC） 稳压器 - DC-DC 开关稳压器

封装/外壳：8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 功能：降压 包装：卷带（TR） 描述：IC REG BUCK ADJ 1.5A 8MSOP 集成电路（IC） DC DC 开关稳压器

DUAL 64-STAGE STATIC SHIFT REGISTER

DESCRIPTION The HCC4517B (extended temperature range) and HCF4517B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package. ■ CLOCK FREQUENCY 12MHz (TYP.) AT VDD = 10V ■ SCHMITT TRIGGER CLOCK INPUTS ALLOW OPERATION WITH V

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp