Introduction

The VRC5074 System Controller is a software-configurable chip that directly connects

the VR5000 CPU to SDRAM memory, a PCI Bus, and a Local Bus, without external

logic or buffering. From the CPU’s viewpoint, the controller acts as a memory controller,

DMA controller, PCI-Bus host bridge, and Local-Bus host bridge. From the viewpoint

of PCI agents, the controller acts as master and target on the PCI Bus. The

controller also has one serial port and four timers.

‰ CPU Interface

• Connects directly to a 250 MHz VR5000 CPU.

• 100 MHz CPU bus.

• Peak block-transfer throughput of 800 Mbytes/sec, maximum sustained

throughput of 640 Mbytes/sec.

• 16 x 8-byte (128-byte) CPU-to-controller FIFO.

• Little-endian or big-endian byte order on CPU interface.

• Supports secondary cache.

• 15 interrupt sources, individually enabled and assigned to one of the CPU’s

seven interrupt inputs.

• Supports all CPU bus-cycle types (but the only write type is pipelined write).

Parity generation and checking on CPU data cycles.

• Mode data at reset provided by a serial EEPROM or by the controller.

• 3.3V I/O.

‰ Memory Interface

• 100 MHz memory bus.

• Maximum sustained throughput of 800 Mbytes/sec.

• Supports three physical loads per data bit: two SDRAM physical banks and

one other (e.g., EPROM, Flash, or buffers bridging to a secondary memory

bus).

• Supports four types of SDRAM with two to four on-chip virtual banks: 256Mb

four-bank, 64Mb four-bank, 64Mb two-bank, 16Mb two-bank.

• On-chip bank-interleaving buffers.

• Programmable address ranges for each memory bank.

• Memory may maintain multiple open SDRAM pages.

• Parity or ECC generation and checking of memory data cycles with 64+8 bits

of SDRAM and no performance degradation.