FEATURES

• On-chip clock recovery/clock synthesis functions

• Provides TC sub-layer function for the ATM protocol’s physical layer

• Supported frame formats include 155 Mbps SONET STS-3c/SDH STM-1

• Conforms to ATM Forum UTOPIA interface Level 2 V1.0 (af-phy-0039.000 June 1995)

Supports three UTOPIA interfaces:

• Single PHY octet-level handshaking

• Single PHY cell-level handshaking

• Multi PHY mode

• Selectable to drop/bypass unassigned cells

• On-chip internal loopback functions for PMD layer loopback and ATM layer loopback

• Supports two PMD interfaces: serial and parallel

• 155.52 Mbps serial interface

• 19.44 MHz parallel interface

• Provides registers for writing/reading overhead information

SOH (section overhead) :J0 byte, Z0 (first and second) bytes, F1 byte

LOH (line overhead) :K1 byte, K2 byte

POH (path overhead) :F2 byte, C2 byte, H4 byte

• Provides pseudo error frame transmit function for various errors

• Supports JTAG boundary scan test function (IEEE 1149.1)

• CMOS technology

• +3.3 V single power supply