• 32-bit RISC CPU with Harvard Architecture

• 256 kB Flash, 12 kB RAM

• Full-CAN Interface: 5 channels

• Serial Interfaces: 6 channels

- 3-wire mode: 3 channels

- UART mode: 2 channels

- I²C mode: 1 channel

• Timers: 3 channels

- 16-bit multi purpose timer/event counter:

channels: 3 channels

• 10-bit resolution A/D Converter: 4 channels

• Non-Multiplexed External Bus Interface (16-/8-bit

data / 20-bit address)

• I/O lines: max. 80