• 32-bit RISC CPU with Harvard Architecture

• Internal ROM: 128 KB

• Internal RAM: 6 KB

• CAN Interface: 1 channel (AFCAN)

• Serial Interfaces: 4 channels

- clocked serial: 2 channels (CSIB)

- UARTA: 2 channels (LIN compatible)

• Timers: 6 channels

- 16-bit interval timer: 1 channel (TMM)

- 16-bit timer/event counter: 2 channels (TMP)

- 16-bit timer/event counter: 1 channel (TMQ)

- Watch timer: 1 channel

- Watchdog timer: 1 channel (WDT2)

• 10-bit resolution A/D Converter: 10 channels

• GPIO: 60 I/O, 8 O